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asahi kasei [AK4527] m0079-e-00 1999/10 - 1 - general description the AK4527 is a single chip codec that includes two channels of adc and six channels of dac. the adc outputs 24bit data and the dac accepts up to 24bit input data. the adc has the enhanced dual bit architecture with wide dynamic range. the dac introduces the new developed advanced multi-bit architecture, and achieves wider dynamic range and lower outband noise. an auxiliary digital audio input interface maybe used instead of the adc for passing audio data to the primary audio output port. control may be set directly by pins or programmed through a separate serial interface. the AK4527 has a dynamic range of 102db for adc, 106db for dac and is well suited for digital surround for home theater and car audio. an ac-3 system can be built with a iec958(spdif) receiver such as the ak4112. the AK4527 is available in a small 44pin lqfp package which will reduce system space. *ac-3 is a trademark of dolby laboratories. features o 2ch 24bit adc - 64x oversampling - sampling rate up to 96khz - linear phase digital anti-alias filter - differential inputs with single-ended use capability - s/(n+d): 92db - dynamic range, s/n: 102db - digital hpf for offset cancellation - i/f format: msb justified or i 2 s o 6ch 24bit dac - 128x oversampling - sampling rate up to 96khz - 24bit 8 times digital filter - single-ended outputs - on-chip switched-capacitor filter - s/(n+d): 90db - dynamic range, s/n: 106db - i/f format: msb justified, lsb justified(20bit,24bit) or i 2 s - individual channel digital volume with 256 levels and 0.5db step - soft mute o de-emphasis for 32khz, 44.1khz and 48khz o zero detect function o high jitter tolerance o ttl level digital i/f o 3-wire serial and i 2 c bus p i/f for mode setting o master clock:256fs, 384fs or 512fs for fs=32khz to 48khz 128fs, 192fs or 256fs for fs=64khz to 96khz o power supply: 4.5 to 5.5v o power supply for output buffer: 2.7 to 5.5v o small 44pin lqfp high performance multi-channel audio codec AK4527
asahi kasei [AK4527] m0079-e-00 1999/10 - 2 - n block diagram audio i/f lpf lpf dac datt lpf dac datt lpf dac datt lpf dac datt lpf dac datt lout1 rout1 lout2 rout2 lout3 rout3 dac datt AK4527 adc hpf adc hpf rin- rin+ lin- lin+ lrck bick sdout1 sdout2 sdout3 ac3 sdin mck o lrck bick xti xto dir sdto ak4112 rx4 rx3 rx2 rx1 lrck bick sdti1 sdti2 sdti3 daux sdos mclk lrck bick sdout sdin1 sdin2 sdin3 mclk sdto format converter block diagram (dir and ac-3 dsp are external parts)
asahi kasei [AK4527] m0079-e-00 1999/10 - 3 - n ordering guide AK4527vq -40 ~ +85 c 44pin lqfp(0.8mm pitch) akd4527 evaluation board for AK4527 n pin layout s dos loop1 1 i2c 44 2 s mute 3 bick 4 lrck 5 s dti1 6 s dti2 7 s dti3 8 s dto 9 daux 10 dfs 11 loop0/sda/cdti 43 dif1/scl/cclk 42 41 40 mclk 39 dzf1 38 avss 37 avdd 36 vrefh 35 vcom 34 dem1 12 dem0 13 tvdd 14 dvdd 15 dvss 16 17 icks2 18 icks1 19 icks0 20 cad1 21 cad0 22 33 32 31 30 29 28 27 26 25 24 23 dzf2 rin+ rin- lin+ lin- rout1 lout1 rout2 lout2 rout3 lout3 AK4527vq top view pdn dif0/csn p/s
asahi kasei [AK4527] m0079-e-00 1999/10 - 4 - n compatibility with ak4526a 1. changed specs ak4526a AK4527 power supply for output buffer no yes adc: resolution fs(max) 20bit 48khz 24bit 96khz dac: dr, s/n 100db 106db output volume analog 20db span 1db step digital 127db span 0.5db step (soft transition) xtal oscillating circuit yes no master clock output yes no master mode yes no de-emphasis daux 32/44.1/48/96khz each dac 32/44.1/48khz mute analog digital soft mute zero detect no yes timing reset no yes p i/f 4-wire serial 3-wire serial, i 2 c bus adc,dac individual power down no yes 2. pin compatibility the following pin fun ctions are changed from ak4526a. but when xtal oscillating circuit is not used, it is possible to change ak4526a to AK4527 without changing the board layout. pin# ak4526a AK4527 2ocks i2c 3m/s smute 14 mcko tvdd 18 xts icks2 33 vrefl dzf2 38 xti dzf1 39 xto/mcki mclk 42 cclk/dif1 dif1/scl/cclk 43 cdti/loop0 loop0/sda/cdti 44 cdto/loop1 loop1
asahi kasei [AK4527] m0079-e-00 1999/10 - 5 - 3. change of layout from ak4526a to AK4527 note: this figure shows only the change of the layout from the ak4526a(external clock mode) to the AK4527. pin# ak4526a AK4527 mcko tvdd 14 open. connected to 5v or 3.3v. vrefl dzf2 33 connected to avss. open, or connected to the external mute circuit. cdto/loop1 loop1 44 open or connected to p port. connected to dvss (or dvdd). 4. change of external circuit from ak4526a to AK4527 external circuit of single-ended input changes as the following figure. loop1 43 42 41 40 39 38 37 36 35 34 sdos 1 2 3 4 5 6 7 8 9 11 10 i2c bick lrck sdti1 sdti2 sdti3 sdto daux dfs rin+ cdti cclk mclk dzf1 avss vrefh avdd vcom dem1 dzf2 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 dvdd dem0 tvdd dvss icks2 icks1 icks0 cad1 cad0 rin- lin+ lin- rout1 lout1 rout2 lout2 rout3 lout3 AK4527 pdn csn p/s smute 44 10f 0.1f 5v 5v 0.1f 10f cdto 43 42 41 40 39 38 37 36 35 34 sdos 1 2 3 4 5 6 7 8 9 11 10 ocks bick lrck sdti1 sdti2 sdti3 sdto daux dfs rin+ cdti cclk mcki xti avss vrefh avdd vcom dem1 vrefl 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 dvdd dem0 mcko dvss xts icks1 icks0 cad1 cad0 rin- lin+ lin- rout1 lout1 rout2 lout2 rout3 lout3 ak4526a pdn csn p/s m/sn 44 10f 0.1f 5v 5v 0.1f 10f ak4526a 2.2nf 470 + signal 0.1u 10u 3.0vpp 32 31 30 29 rin+ rin- lin- lin+ 4.7u same circuit AK4527 2.2nf 470 + signal 470 0.1u 22u 4.7k 3.0vpp 32 31 30 29 rin+ rin- lin- lin+ avdd 4.7k 10u bias same circuit
asahi kasei [AK4527] m0079-e-00 1999/10 - 6 - pin/function no. pin name i/o function 1 sdos i sdto source select pin (note 1) l: internal adc output, h: daux input 2 i2c i control mode select pin l: 3-wire serial, h: i 2 c bus 3 smute i soft mute pin (note 1) when this pin goes to h, soft mute cycle is initialized. when returning to l, the output mute releases. 4 bick i audio serial data clock pin 5 lrck i input channel clock pin 6 sdti1 i dac1 audio serial data input pin 7 sdti2 i dac2 audio serial data input pin 8 sdti3 i dac3 audio serial data input pin 9 sdto o audio serial data output pin 10 daux i aux audio serial data input pin 11 dfs i double speed sampling mode pin (note 1) l: normal speed, h: double speed 12 dem1 i de-emphasis 1 pin (note 2) 13 dem0 i de-emphasis 0 pin (note 2) 14 tvdd - output buffer power supply pin, 2.7v ~ 5.5v 15 dvdd - digital power supply pin, 4.5v ~ 5.5v 16 dvss - digital ground pin, 0v 17 pdn i power-down & reset pin when l, the AK4527 is powered-down and the control registers are reset to default state. if the state of cad0-1 changes, then the AK4527 must be reset by pdn. 18 icks2 i input clock select 2 pin (note 1) this pin should be connected to dvss. 19 icks1 i input clock select 1 pin (note 1) 20 icks0 i input clock select 0 pin (note 1) 21 cad1 i chip address 1 pin 22 cad0 i chip address 0 pin
asahi kasei [AK4527] m0079-e-00 1999/10 - 7 - no. pin name i/o function 23 lout3 o dac3 lch analog output pin 24 rout3 o dac3 rch analog output pin 25 lout2 o dac2 lch analog output pin 26 rout2 o dac2 rch analog output pin 27 lout1 o dac1 lch analog output pin 28 rout1 o dac1 rch analog output pin 29 lin- i lch analog negative input pin 30 lin+ i lch analog positive input pin 31 rin- i rch analog negative input pin 32 rin+ i rch analog positive input pin 33 dzf2 o zero input detect 2 pin (note 3) when the input data of the group 1 follow total 8192 lrck cycles with 0 input data, this pin goes to h. this pin is always l if p/s = h. 34 vcom o common voltage output pin, avdd/2 large external capacitor around 2.2fis used to reduce power-supply noise. 35 vrefh i positive voltage reference input pin, avdd 36 avdd - analog power supply pin, 4.5v ~ 5.5v 37 avss - analog ground pin, 0v 38 dzf1 o zero input detect 1 pin (note 3) when the input data of the group 1 follow total 8192 lrck cycles with 0 input data, this pin goes to h. this pin is always l if p/s = h. 39 mclk i master clock input pin 40 p/s i parallel/serial select pin l: serial control mode, h: parallel control mode dif0 i audio data interface format 0 pin in parallel control mode 41 csn i chip select pin in 3-wire serial control mode this pin should be connected to dvdd at i 2 c bus control mode dif1 i audio data interface format 1 pin in parallel control mode 42 scl/cclk i control data clock pin in serial control mode i2c = l: cclk (3-wire serial), i2c = h: scl (i 2 c bus) loop0 i loopback mode 0 pin in parallel control mode enables digital loop-back from adc to 3 dacs. 43 sda/cdti i/o control data input pin in serial control mode i2c = l: cdti (3-wire serial), i2c = h: sda (i 2 c bus) 44 loop1 i loopback mode 1 pin (note 1) enables all 3 dac channels to be input from sdti1. notes: 1. sdos, smute, dfs, icks2-0 and loop1 pins are ored with register data if p/s = l. 2. dem1-0 pins are ored with register data of dema1-c0 bits if p/s = l. dem1 pin = h: dema1 = demb1 = demc1 = 1, dem0 pin = h: dema0 = demb0 = demc0 = 1. 3. the group 1 and 2 can be selected by dzfm2-0 bits if p/s = l. 4. all input pins should not be left floating.
asahi kasei [AK4527] m0079-e-00 1999/10 - 8 - absolute maximum ratings (avss, dvss=0v; note 5) parameter symbol min max units power supplies analog digital output buffer |avss-dvss| (note 6) avdd dvdd tvdd d gnd -0.3 -0.3 -0.3 - 6.0 6.0 6.0 0.3 v v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c notes: 5. all voltages with respect to ground. 6. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 5) parameter symbol min typ max units power supplies (note 7) analog digital output buffer avdd dvdd tvdd 4.5 4.5 2.7 5.0 5.0 5.0 5.5 5.5 5.5 v v v notes: 5. all voltages with respect to ground. 7. the power up sequence between avdd, dvdd and tvdd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4527] m0079-e-00 1999/10 - 9 - analog characteristics (ta=25 c; avdd, dvdd, tvdd=5v; avss, dvss=0v; vrefh=avdd; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz ~ 20khz at 44.1khz, 20hz~40khz at fs=96khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: differential inputs; analog source impedance=470 w resolution 24 bits s/(n+d) (-0.5dbfs) (note 8) fs=44.1khz fs=96khz 84 78 92 88 db db dr (-60dbfs) fs=44.1khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db s/n (note 9) fs=44.1khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.3 db gain drift 20 - ppm/ c input voltage ain=0.6xvrefh (note 10) 2.85 3.0 3.15 vpp input resistance (note 11) 18 28 k w power supply rejection (note 12) 50 db dac analog output characteristics: resolution 24 bits s/(n+d) fs=44.1khz fs=96khz 80 78 90 88 db db dr (-60dbfs) fs=44.1khz, a-weighted fs=96khz fs=96khz, a-weighted 95 88 94 106 100 106 db db db s/n (note 13) fs=44.1khz, a-weighted fs=96khz fs=96khz, a-weighted 95 88 94 106 100 106 db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6xvrefh 2.75 3.0 3.25 vpp load resistance 5 k w power supply rejection (note 12) 50 db power supplies power supply current (avdd+dvdd+tvdd) normal operation (pdn = h) avdd dvdd+tvdd fs=44.1khz (note 14) fs=96khz power-down mode (pdn = l) (note 15) 35 25 35 10 56 40 56 100 ma ma ma a notes: 8. in case of single ended input, s/(n+d)=80db(typ, @avdd=5v, fs=44.1khz). 9. s/n measured by ccir-arm is 98db(@fs=44.1khz). 10. full scale input for each ain+/- pin is 1.5vpp in differential mode. 11. input resistance is 14k w typically at fs=96khz. 12. psr is applied to avdd, dvdd and tvdd with 1khz, 50mvpp. vrefh pin is held a constant voltage. 13. s/n measured by ccir-arm is 102db(@fs=44.1khz). 14. dvdd=24.9ma, tvdd=0.1ma(typ). 15. in the power-down mode. all digital input pins including clock pins (mclk, bick, lrck) are held dvss.
asahi kasei [AK4527] m0079-e-00 1999/10 - 10 - filter characteristics (ta=25 c; avdd, dvdd=4.5 ~ 5.5v; tvdd=2.7 ~ 5.5v; fs=44.1khz; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 16) -0.005db -0.02db -0.06db -6.0db pb 0 - - - 20.02 20.20 22.05 19.76 - - - khz khz khz khz stopband sb 24.34 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 17) gd 27.6 1/fs group delay distortion d gd 0s adc digital filter (hpf): frequency response (note 16) -3db -0.5db -0.1db fr 0.9 2.7 6.0 hz hz hz dac digital filter: passband (note 16) -0.1db -6.0db pb 0 - 22.05 20.0 - khz khz stopband sb 24.2 khz passband ripple pr 0.02 db stopband attenuation sa 56 db group delay (note 16) gd 21.9 1/fs dac digital filter + analog filter: frequency response: 0 ~ 20.0khz 40.0khz (note 18) fr fr 0.2 0.3 db db notes: 16. the passband and stopband frequencies scale with fs. for example, 20.02khz at C0.02db is 0.454 x fs. the reference frequency of these responses is 1khz. 17. the calculating delay time which occurred by digital filtering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 18. fs=96khz.
asahi kasei [AK4527] m0079-e-00 1999/10 - 11 - digital characteristics (ta=25 c; avdd, dvdd=4.5 ~ 5.5v; tvdd=2.7 ~ 5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (sdto pin: iout=-100a) (dzf1, dzf2 pins: iout=-100a) low-level output voltage (sdto, dzf1, dzf2 pins: iout= 100a) (sda pin: iout= 3ma) voh voh vol vol tvdd-0.5 avdd-0.5 - - - - - - - - 0.5 0.4 v v v v input leakage current iin - - 10 a switching characteristics (ta=25 c; avdd, dvdd=4.5 ~ 5.5v; tvdd=2.7 ~ 5.5v; c l =20pf) parameter symbol min typ max units master clock input 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck frequency normal speed mode (dfs = 0) double speed mode (dfs = 1) duty cycle fsn fsd duty 32 64 45 48 96 55 khz khz % audio interface timing bick period bick pulse width low pulse width high lrck edge to bick - (note 19) bick - to lrck edge (note 19) lrck to sdto(msb) bick to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 160 65 65 45 45 40 25 40 40 ns ns ns ns ns ns ns ns ns notes: 19. bick rising edge must not occur at the same time as lrck edge.
asahi kasei [AK4527] m0079-e-00 1999/10 - 12 - parameter symbol min typ max units control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn h time csn to cclk - cclk - to csn - rise time of csn fall time of csn rise time of cclk fall time of cclk tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tr1 tf1 tr2 tf2 200 80 80 40 40 0.025*1/fs 50 50 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 20) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz m s m s m s m s m s m s m s m s m s m s m s power-down & reset timing pdn pulse width (note 21) pdn - to sdto valid (note 22) tpd tpdv 150 516 ns 1/fs notes: 20. data must be held for sufficient time to bridge the 300 ns transition time of scl. 21. the AK4527 can be reset by bringing pdn l to h upon power-up. 22. these cycles are the number of lrck rising from pdn rising.
asahi kasei [AK4527] m0079-e-00 1999/10 - 13 - n timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tlrs sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing
asahi kasei [AK4527] m0079-e-00 1999/10 - 14 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing (3-wire serial) csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing (3-wire serial) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn tpdv sdto 50%tvdd vih power-down & reset timing
asahi kasei [AK4527] m0079-e-00 1999/10 - 15 - operation overview n system clock the master clock can be external ttl level clock input to the mclk pin. the relationship between the master clock and the desired sample rate is defined in table 1. the sampling rate corresponds to 32khz ~ 48khz at normal speed mode (dfs = 0) and 64khz ~ 96khz (dfs = 1). dfs pin and icks2-0 pins should be changed in the power-down mode (pdn = l) at parallel control mode. mclk speed, dfs pin and icks2-0 bits should be changed when rstn bit is 0 at serial control mode. mclk should be synchronized with lrck but the phase is not critical. external clocks (mclk, bick) should always be present whenever the AK4527 is in normal operation mode (pdn = h). if these clocks are not provided, the AK4527 may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4527 should be in the power-down mode (pdn = l) or in the reset mode (rstn = 0). after exiting reset at power-up etc., the AK4527 is in the power-down mode until mclk and lrck are input. mclk mode icks2 icks1 icks0 dfs = 0 dfs = 1 00 0 0 256fs 128fs 1 0 0 1 384fs 192fs 2 0 1 0 512fs 256fs 3 0 1 1 256fs 256fs 41 0 0n/an/a 51 0 1n/an/a default (dfs = 0) table 1. master clock frequency select (note: at double speed mode(dfs = 1), mode 0 and 1 are not available for adc.) n de-emphasis filter the AK4527 includes the digital de-emphasis filter (tc=50/15s) by iir filter. this filter corresponds to four sampling frequencies (32khz, 44.1khz, 48khz). in parallel control mode (p/s = h), de-emphasis mode is selected by the dfs, dem1 and dem0 pins. in serial control mode (p/s = l), de-emphasis of each dac can be set individually by register data of dema1-c0 (dac1: dema1-0, dac2: demb1-0, dac3: demc1-0, see register definitions). dem1-0 pins are ored with register: dem1 = h: dema1 = demb1 = demc1 = 1 dem0 = h: dema0 = demb0 = demc0 = 1 mode dfs dem1 dem0 dem 0 0 0 0 44.1khz 10 0 1off 2 0 1 0 48khz 3 0 1 1 32khz 41 0 0off 51 0 1off 61 1 0off 71 1 1off default table 2. de-emphasis control
asahi kasei [AK4527] m0079-e-00 1999/10 - 16 - n digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 0.9hz at fs=44.1khz and also scales with sampling rate (fs). n audio serial interface format four serial data modes can be selected by the dif0 and dif1 pins (p/s = h) or bits (p/s = l) as shown in table 3. in all modes the serial data is msb-first, 2s compliment format. the sdto is clocked out on the falling edge of bick and the sdti/daux are latched on the rising edge of bick. figures 3 ~ 6 shows the timing at sdos = l. in this case, the sdto outputs the adc output data. when sdos = h, the data input to daux is converted to sdtos format and output from sdto. mode 2 and mode 3 in sdti/daux input formats can be used for 16-20bit data by zeroing the unused lsbs. mode dif1 dif0 sdto sdti1, sdti2, sdti3, daux lrck 0 0 0 24bit, msb justified 20bit, lsb justified h/l 1 0 1 24bit, msb justified 24bit, lsb justified h/l 2 1 0 24bit, msb justified 24bit, msb justified h/l 3 1 1 24bit, iis (i2s) 24bit, iis (i2s) l/h default table 3. audio data formats
asahi kasei [AK4527] m0079-e-00 1999/10 - 17 - lrck bick(64fs) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data dont care dont care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 3. mode 0 timing lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data dont care dont care 16 15 14 figure 4. mode 1 timing lrck bick(64fs) sdto ( o ) 0 1 2 18192021 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data dont care 2 21 28 29 30 23 0 19 20 21 31 1 0 dont care 2 21 28 29 30 0 figure 5. mode 2 timing lrck bick(64fs) sdto ( o ) 0 1 2 3 23 24 25 26 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data dont care 2 21 0 2 3 23 24 25 26 0 31 29 30 23 22 1 22 23 0 dont care 2 21 0 1 figure 6. mode 3 timing
asahi kasei [AK4527] m0079-e-00 1999/10 - 18 - n zero detection the AK4527 has two pins for zero detect flag outputs. dzf1 pin corresponds to the group 1 channels and dzf2 pin corresponds to the group 2 channels. this grouping is selected by dzfm2-0 bits (see table 4). for example, in mode 0, dzf1 is and of all 6 channels and dzf2 is disable (l). when the input data of all channels in the group 1(group 2) are continuously zeros for 8192 lrck cycles, dzf1(dzf2) pin goes to h. dzf1(dzf2) pin immediately goes to l if input data of any channels in the group 1(group 2) is not zero after going dzf1(dzf2) h. zero detection is always disable at parallel control mode(p/s = h). mode dzfm2 dzfm1 dzfm0 lout1 rout1 lout2 rout2 lout3 rout3 0 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 1 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 2 0 1 0 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 3 0 1 1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 4 1 0 0 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 5 1 0 1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 6 1 1 0 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 7 1 1 1 disable (dzf1 = dzf2 = l) default table 4. zero detect control
asahi kasei [AK4527] m0079-e-00 1999/10 - 19 - n soft mute operation soft mute operation is performed at digital domain. when the smute pin goes to h, the output signal is attenuated by - during 1024 lrck cycles. when the smute pin is returned to l, the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute attenuation dzf1 1024/fs 0db - aout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the output signal is attenuated by - during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input have the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. (4) when the input data of all channels in the group 1 are continuously zeros for 8192 lrck cycles, dzf1 pin goes to h. dzf1 pin immediately goes to l if input data of any channel in the group 1 is not zero after going dzf1 h. figure 7. soft mute and zero detection n system reset the AK4527 should be reset once by bringing pdn = l upon power-up. the AK4527 is powered up and the internal timing starts clocking by lrck - after exiting reset and power down state by mclk. the AK4527 is in the power-down mode until mclk and lrck are input.
asahi kasei [AK4527] m0079-e-00 1999/10 - 20 - n power-down the adc and dacs of AK4527 are placed in the power-down mode by bringing pdn l and both digital filters are reset at the same time. pdn l also reset the control registers to their default values. in the power-down mode, the analog outputs go to hi-z and dzf1-2 pins go to l. this reset should always be done after power-up. in case of the adc, an analog initialization cycle starts after exiting the power-down mode. therefore, the output data, sdto becomes available after 516 cycles of lrck clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are hi-z during the initialization. figure 8 shows the power-up sequence. the adc and dacs can be powered-down individually by pwadn and pwdan bits. in this case, the internal register values are not initialized. when pwadn = 0, sdto goes to l. when pwdan = 0, the analog outputs go to hi- z and dzf1-2 pins go to h. because some click noise occurs, the analog output should muted externally if the click noise influences system application. adc internal state pdn 516/fs normal operation power-down init cycle normal operation (1) dont care gd gd clock in mclk,lrck,sclk adc in (analog) 0data adc out (digital) normal operation power-down normal operation dac internal state 0data dac in (digital) dac out (analog) gd external mute mute on gd (3) (3) (4) (5) (6) (6) (9) 512/fs init cycle (2) dzf1/dzf2 (7) (8) notes: (1) the analog part of adc is initialized after exiting the power-down state. (2) the analog part of dac is initialized after exiting the power-down state. (3) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (4) adc output is 0 data at the power-down state. (5) click noise occurs at the end of initialization of the analog part. please mute the digital output externally if the click noise influences system application. required muting time depends on the configuration of the input buffer circuits. figure 12,13: 1s figure 14,15: 200ms (6) click noise occurs at the falling edge of pdn and at 512/fs after the rising edge of pdn. (7) when the external clocks (mclk, bick and lrck) are stopped, the AK4527 should be in the power-down mode. (8) dzf pins are l in the power-down mode (pdn = l). (9) please mute the analog output externally if the click noise (6) influences system application. figure 8. power-down/up sequence example
asahi kasei [AK4527] m0079-e-00 1999/10 - 21 - n reset function when rstn = 0, adc and dacs are powered-down but the internal register are not initialized. the analog outputs go to vcom voltage, dzf1-2 pins go to h and sdto pin goes to l. because some click noise occurs, the analog output should muted externally if the click noise influences system application. figure 9 shows the power-up sequence. adc internal state rstn bit normal operation digital block power-down normal operation dont care gd gd clock in mclk,lrck,sclk adc in (analog) 0data adc out (digital) normal operation normal operation dac internal state 0data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 (7) internal rstn bit digital block power-down 2~3/fs (9) 3~4/fs (9) 2/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of adc is initialized after exiting the reset state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is 0 data at the power-down state. (4) click noise occurs when the internal rstn bit becomes 1. please mute the digital output externally if the click noise influences system application. required muting time depends on the configuration of the input buffer circuits. figure 12,13: 1s figure 14,15: 200ms (5) the analog outputs go to vcom voltage. (6) click noise occurs at 3 ~ 4/fs after rstn bit becomes 0, and occurs at 2 ~ 3/fs after rstn bit becomes 1. this noise is output even if 0 data is input. (7) when the external clocks (mclk, bick and lrck) are stopped, the AK4527 should be in the reset mode. (8) dzf pins go to h when the rstn bit becomes 0, and go to l at 4~5/fs after rstn bit becomes 1. (9) there is a delay, 3~4/fs from rstn bit 0 to the internal rstn bit 0, and 2~3/fs from rstn bit 1 to the internal rstn bit 1. figure 9. reset sequence example
asahi kasei [AK4527] m0079-e-00 1999/10 - 22 - n serial control interface the AK4527 can control its functions via pins or registers. the serial control interface is enabled by the p/s pin = l. internal registers may be written by 2 types of control mode. the chip address is determined by the state of the cad0 and cad1 inputs. pdn = l initializes the registers to their default values. writing 0 to the rstn bit can initialize the internal timing circuit. but in this case, the register data is not be initialized. (1) 3-wire serial control mode (i2c = l) internal registers may be written to the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). the csn and cclk pins should be held to h except for access. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 1 : write only) a4-a0: register address d7-d0: control data (2) i 2 c bus control mode (i2c = h) internal registers may be written to i 2 c bus interface pins (scl and sda). the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of scl and data is clocked out on the falling edge. data can be written after a high-to-low transition of sda when scl is h(start condition), and is latched after a low-to-high transition of sda when scl is h(stop condition). the clock speed of scl is 100khz(max). the csn pin should be connected to dvdd at i 2 c bus control mode. scl sda 0 0100 r/w start stop ack ack ack c1 c0 0 0 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 1 : write only) a4-a0: register address d7-d0: control data ack: acknowledge note: writing to control register is invalid when pdn = l or the mclk is not fed.
asahi kasei [AK4527] m0079-e-00 1999/10 - 23 - n mapping of program registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif1 dif0 0 smute 01h control 2 0 0 loop1 loop0 sdos dfs 0 0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 08h de-emphasis 0 0 dema1 dema0 demb1 demb0 demc1 demc0 09h clock mode 0 0 0 0 icks2 icks1 icks0 rstn 0ah zero detect 0 0 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan note: for addresses from 0bh to 1fh, data is not written. when pdn goes to l, the registers are initialized to their default values. when rstn bit goes to 0, the internal timing is reset and dzf1-2 pins go to h, but registers are not initialized to their default values. (when zero detection is disable, dzf1-2 pins do not change.) smute, icks2-0, dfs, sdos and loop1 are ored with pins.
asahi kasei [AK4527] m0079-e-00 1999/10 - 24 - n n n n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif1 dif0 0 smute default 00000000 smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted register bit of smute is ored with the smute pin if p/s = l. dif1-0: audio data interface modes (see table 3.) initial: 00, mode 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 loop1 loop0 sdos dfs 0 0 default 00000000 dfs: sampling speed mode (see table 1.) 0: normal speed 1: double speed register bit of dfs is ored with dfs pin if p/s = l. sdos: sdto source select 0: adc 1: daux register bit of sdos is ored with sdos pin if p/s = l. loop1-0: loopback mode enable 00: normal (no loop back) 01: lin ? lout1, lout2, lout3 rin ? rout1, rout2, rout3 the digital adc output (daux input if sdos = 1) is connected to the digital dac input. in this mode, the input dac data to sdti1-3 is ignored. when the audio format is set mode 1 at loopback mode, the audio format of sdto becomes mode 3. 10: sdti1(l) ? sdti2(l), sdti3(l) sdti1(r) ? sdti2(r), sdti3(r) in this mode the input dac data sdti2 and sdti3 are ignored. 11: n/a register bit of loop1 is ored with loop1 pin if p/s = l.
asahi kasei [AK4527] m0079-e-00 1999/10 - 25 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 default 00000000 att7-0: attenuation level 256 levels, 0.5db step att7-0 attenuation 00h 0db 01h -0.5db 02h -1.0db : : : : fdh -126.5db feh -127.0db ffh mute (- ) the transition between set values is soft transition of 7425 levels. it takes 7424/fs (168ms@fs=44.1khz) from 00h(0db) to ffh(mute). if pdn pin goes to l, the atts are initialized to 00h. the atts are 00h when rstn = 0. when rstn return to 1, the atts fade to their current value. digital attenuator is independent of soft mute function. addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h de-emphasis 0 0 dema1 dema0 demb1 demb0 demc1 demc0 default 00000000 dema1-0: de-emphasis response control for dac1 data on sdti1 (see table 2.) initial: 00, 44.1khz demb1-0: de-emphasis response control for dac2 data on sdti2 (see table 2.) initial: 00, 44.1khz demc1-0: de-emphasis response control for dac3 data on sdti3 (see table 2.) initial: 00, 44.1khz
asahi kasei [AK4527] m0079-e-00 1999/10 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h clock mode 0 0 0 0 icks2 icks1 icks0 rstn default 00000001 rstn: internal timing reset 0: reset. dzf1-2 pins go to h, but registers are not initialized. 1: normal operation when the state of dif2-0,icks2-0 or dfs changes, the AK4527 should be reset by pdn pin or rstn bit. some click noise occurs at that timing. icks2-0: master clock frequency select (see table 1.) initial: 00, mode 0 register bits of icks2-0 are ored with the icks2-0 pins if p/s = l. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah zero detect 0 0 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan default 00111 1 1 1 pwdan: power-down control of dac1-3 0: power-down 1: normal operation pwadn: power-down control of adc 0: power-down 1: normal operation pwvrn: power-down control of reference voltage 0: power-down 1: normal operation dzfm2-0: zero detect mode select (see table 4.) initial: 111, disable
asahi kasei [AK4527] m0079-e-00 1999/10 - 27 - system design figure 10 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: tvdd=5v, serial control mode, i 2 c bus control mode, cad1-0 = 00, dzfm2-0 = 000 loop1 44 43 42 41 40 39 38 37 36 35 34 sdos 1 2 3 4 5 6 7 8 9 11 10 i2c bick lrck sdti1 sdti2 sdti3 sdto daux dfs rin+ sda scl mclk dzf1 avss vrefh avdd vcom dem1 dzf2 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 dvdd dem0 tvdd dvss icks2 icks1 icks0 cad1 cad0 rin- lin+ lin- rout1 lout1 rout2 lout2 rout3 lout3 AK4527 + 0.1 0.1 2.2 + 5 p analog ground digital ground (dir) dsp analog 5v + 10 audio (mpeg/ ac3) digital audio source 1n 1n 470 pdn csn p/s smute 0.1 10 470 470 470 mute mute mute mute mute mute power-down control figure 10. typical connection diagram
asahi kasei [AK4527] m0079-e-00 1999/10 - 28 - analog ground digital ground system controller loop1 sdos 1 2 3 4 5 6 7 8 9 11 10 i2c bick lrck sdti1 sdti2 sdti3 sdto daux dfs rin+ sda scl mclk dzf1 avss vrefh avdd vcom dem1 dzf2 12 13 14 15 16 17 18 19 20 21 22 dvdd dem0 tvdd dvss icks2 icks1 icks0 cad1 cad0 rin- lin+ lin- rout1 lout1 rout2 lout2 rout3 lout3 AK4527 pdn csn p/s smute 33 32 31 30 29 28 27 26 25 23 24 44 43 42 41 40 39 38 37 36 35 34 figure 11. ground layout note: avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling the AK4527 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK4527 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4527 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of vrefh sets the analog input/output range. vrefh pin is normally connected to avdd with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vrefh and vcom pins in order to avoid unwanted coupling into the AK4527. 3. analog inputs the adc inputs are differential. figures 12 and 13 are circuit examples which analog signal is input by single end. the signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. in case of single ended input, the distortion around full scale degrades compared with differential input. figures 14 and 15 are circuit examples which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x vrefh vpp. the AK4527 can accept input voltages from avss to avdd. the adc output data format is 2s complement. the output code is 7fffffh(@24bit) for input above a positive full scale and 800000h(@24bit) for input below a negative fill scale. the ideal code is 000000h(@24bit) with no input signal. the dc offset is removed by the internal hpf. the AK4527 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. a simple rc filter (fc=150khz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs.
asahi kasei [AK4527] m0079-e-00 1999/10 - 29 - AK4527 2.2nf 470 + signal 470 0.1 22 4.7k 3.0vpp 32 31 30 29 rin+ rin- lin- lin+ avdd 4.7k 10 bias same circuit figure 12. single end input example (not using op-amp) AK4527 2.2nf 470 + vop=avdd=5v signal 10k 470 0.1 22 4.7k 6.4vpp 3.0vpp 32 31 30 29 rin+ rin- lin- lin+ vop 4.7k avdd 4.7k 10 bias same circuit njm2100 + - figure 13. single end input example (using op-amp) AK4527 1nf 470 + vop=avdd=5v signal 10k 470 0.1 22 4.7k 10k 3.2vpp 1.5vpp 32 31 30 29 rin+ rin- lin- lin+ 10k vop 4.7k 4.7k 10 bias same circuit 1.5vpp njm2100 + + - - avdd figure 14. differential input buffer example (using op-amp with single power supply) AK4527 1nf 470 + signal 10k 470 0.1 22 4.7k 10k 3.2vpp 1.5vpp 32 31 30 29 rin+ rin- lin- lin+ 10k +vop 4.7k 4.7k 10 bias same circuit 1.5vpp njm5532 + + - - -vop vop=12v avdd avdd figure 15. differential input buffer example (using op-amp with dual power supply)
asahi kasei [AK4527] m0079-e-00 1999/10 - 30 - 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. the dac input data format is 2s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv. n peripheral i/f example the AK4527 can accept the signal of device with a nominal 3.3v supply because of ttl input. the power supply for output buffer (tvdd) of the AK4527 should be 3.3v when the peripheral devices operate at a nominal 3.3v supply. figure 16 shows an example with the mixed system of 3.3v and 5v. 3.3v analog 5v analog 3.3v digital 5v digital pll i/f audio signal dsp ak4112 analog digital control signal up & others AK4527 5v for input 3.3v for output figure 16. power supply connection example
asahi kasei [AK4527] m0079-e-00 1999/10 - 31 - n applications 1) zoran ac3 decoder, zr38600 analog input analog output sdto sdti1 sdti2 sdti3 lrck bick mclk AK4527 digital input sckin gpio2 spfrx scka wsa sckb wsb sda sdb sdc sdd zr38600 dfs 2) yamaha ac3 decoder, yss912 analog input analog output sdto sdti1 sdti2 sdti3 lrck bick mclk AK4527 digital input 256fs 256fs mcko1 lrck bick sdto rx or ak4112 sdia0 sdbck0 sdwck0 sdia1 sdob0 sdob1 sdob2 yss912 ym3436 3) motorola ac3 decoder, dsp56362 analog input analog output sdto sdti1 sdti2 sdti3 lrck bick mclk AK4527 digital input 256fs 256fs mcko1 lrck bick sdto rx sdi0 sckr fsr sdi1 sdo0 sdo1 sdo2 dsp56362 ak4112 sckt fst
asahi kasei [AK4527] m0079-e-00 1999/10 - 32 - package 0.15 0.17 0.05 0.37 0.10 10.00 1.70max 111 23 33 44pin lqfp ( unit: mm ) 10.00 12.80 0.30 34 44 0.80 22 12 12.80 0.30 0 ~ 0.2 0 ~ 10 0.60 0.20 n n n n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK4527] m0079-e-00 1999/10 - 33 - marking akm AK4527vq xxxxxxx japan 1 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4527vq 4) country of origin 5) asahi kasei logo important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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